III-Nitride based heterojunction field effect transistors (HFETs) are rapidly emerging as the most promising solid-state high-power RF sources since their first demonstration in 1993. Very high power densities, 10-30 W/mm, which are close to the theoretical limits for this material systems, have been achieved in the past two years. One of the most critical issues limiting the performance of these devices at high RF power levels is the device degradation primarily caused by high gate leakage currents. Insulated gate HFETs (IGHFETs) with SiO2 and Si3N4 gate dielectrics can potentially overcome this problem by reducing both the reverse and the forward gate leakage currents by several orders of magnitude. Such insulating gate devices have been reported with much superior stability at high RF power levels as compared to the conventional Schottky gate HFETs.
The insulated gate HFET design leads to a larger threshold voltage. While it has been shown that the RF gain and the knee, voltage for submicron gate IGHFETs are the same as those of submicron HFETs, the larger gate-channel separation in the IGHFETs results in stronger short-channel effects. The reduced gate capacitance further makes IGHFETs more vulnerable to the effects of parasitic circuit capacitances. Thus, the IGHFETs with threshold voltages close to HFETs are very desirable. Such devices can be achieved either by (i) reducing the silicon dioxide or silicon nitride thickness or (ii) by using the materials with higher dielectric permittivity.
The quality of the gate dielectric plays a crucial role in the insulated gate HFET device performance. The presence of interface and bulk charges in the dielectric film adversely affect the gate control by introducing threshold voltage and peak current dispersion. Most of the reported III-N IGHFETs used dielectric layers which are deposited using the Plasma Enhanced Chemical Vapor Deposition (PECVD) technique. This technique produces reasonable quality of dielectric layers when the thicknesses are in excess of 10 nm. However, the PECVD dielectric layers, for thickness less than 10 nm, show increased leakage currents, threshold voltage dispersion and poor reproducibility
As such, a need exists to obtain low threshold IGHFETs with significantly reduced gate leakage currents by reducing the silicon dioxide or silicon nitride thickness.